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PD - 94505
HEXFET(R) Power MOSFET
l
IRFR3410 IRFU3410 ID
31A
Applications High frequency DC-DC converters
VDSS
100V
RDS(on) max
39m
Benefits Low Gate-to-Drain Charge to Reduce Switching Losses l Fully Characterized Capacitance Including Effective COSS to Simplify Design, (See App. Note AN1001) l Fully Characterized Avalanche Voltage and Current
l
D-Pak IRFR3410
I-Pak IRFU3410
Absolute Maximum Ratings
Symbol
VDS VGS ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C PD @TA = 25C dv/dt TJ TSTG
Parameter
Drain-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
100 20 31 22 125 110 3.0 0.71 15 -55 to + 175 300 (1.6mm from case )
Units
V
A W mWC V/ns C
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount)* Junction-to-Ambient
Typ.
--- --- ---
Max.
1.4 40 110
Units
C/W
Notes through are on page 10
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1
9/23/02
IRFR/U3410
Static @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage V(BR)DSS IDSS IGSS Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. 100 --- --- 2.0 --- --- --- --- Typ. --- 0.11 34 --- --- --- --- --- Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 39 m VGS = 10V, ID = 18A 4.0 V VDS = VGS, ID = 250A 20 VDS = 100V, VGS = 0V A 250 VDS = 80V, VGS = 0V, TJ = 150C 200 VGS = 20V nA -200 VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 33 --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- 37 10 11 12 27 40 13 1690 220 26 1640 130 250 Max. Units Conditions --- S VDS = 25V, ID = 18A 56 I D = 18A --- nC VDS = 50V --- VGS = 10V, --- VDD = 50V --- ID = 18A ns --- RG = 9.1 --- VGS = 10V --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 80V, = 1.0MHz --- VGS = 0V, VDS = 0V to 80V
Avalanche Characteristics
Parameter
EAS IAR Single Pulse Avalanche Energy Avalanche Current
Typ.
--- ---
Max.
140 18
Units
mJ A
Diode Characteristics
IS
ISM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 31 showing the A G integral reverse --- --- 125 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 18A, VGS = 0V --- 84 --- ns TJ = 25C, IF = 18A --- 260 --- nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFR/U3410
1000
TOP
VGS
100
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V
TOP
4.5V
10
10
4.5V 20s PULSE WIDTH Tj = 25C
1 0.1 1 10 100
1 0.1 1
20s PULSE WIDTH Tj = 175C
10 100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
RDS(on) , Drain-to-Source On Resistance
ID = 30A VGS = 10V
ID, Drain-to-Source Current ()
100
2.0
10
T J = 25C
(Normalized)
T J = 175C
1.0
1 4.0 5.0 6.0
VDS = 50V 20s PULSE WIDTH
7.0 8.0 9.0
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
T J , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRFR/U3410
100000 VGS = 0V, f = 1 MHZ Ciss = C + Cgd, Cds SHORTED gs Crss = C gd Coss = Cds + Cgd
20 ID= 18A
VGS , Gate-to-Source Voltage (V)
16
10000
VDS = 80V VDS= 50V VDS= 20V
C, Capacitance (pF)
12
Ciss
1000
Coss
100
8
Crss
4
10 1 10 100
0 0 10 20 30 40 50 60 Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000.0
1000
OPERATION IN THIS AREA LIMITED BY RDS (on)
100.0 TJ = 175C 10.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
100sec 10
1msec 1 Tc = 25C Tj = 175C Single Pulse 0.1 1 10 10msec
1.0 TJ = 25C VGS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-toDrain Voltage (V)
100
1000
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFR/U3410
32 LIMITED BY PACKAGE 28
ID , Drain Current (A)
V DS VGS RG VGS
Pulse Width 1 s Duty Factor 0.1 %
RD
D.U.T.
+
24 20 16 12 8 4 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
10% VGS
-VDD
Fig 10a. Switching Time Test Circuit
VDS 90%
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
10
Thermal Response ( Z thJC )
1
D = 0.50 0.20 0.10 0.05 0.02 0.01
0.1
0.01
SINGLE PULSE ( THERMAL RESPONSE )
0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U3410
250
EAS, Single Pulse Avalanche Energy (mJ)
15V
TOP
VDS
L
DRIVER
200
BOTTOM
ID 7.3A 13A 18A
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
150
A
0.01
100
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
50
0 25 50 75 100 125 150 175
Starting TJ , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
VGS
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
IG
ID
Charge
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRFR/U3410
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET(R) Power MOSFETs
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IRFR/U3410
TO-251AA (I-Pak) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 6.22 (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
3X
1.14 (.045) 0.76 (.030)
3X
0.89 (.035) 0.64 (.025) M AMB
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
2.28 (.090) 2X
0.25 (.010)
TO-251AA (I-Pak) Part Marking Information
EXAMPLE: THIS IS AN IRFR120 WIT H ASS EMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 1999 IN THE AS SEMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO
IRF U120 919A 78 56
DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A
AS SEMBLY LOT CODE
8
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IRFR/U3410
TO-252AA (D-Pak) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.094) 2.19 (.086)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 1.27 (.050) 0.88 (.035)
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) MIN. 10.42 (.410) 9.40 (.370) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN -B1.52 (.060) 1.15 (.045) 3X 2X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) M AMB NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 4.57 (.180) 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).
0.58 (.023) 0.46 (.018)
2.28 (.090)
TO-252AA (D-Pak) Part Marking Information
EXAMPLE: THIS IS AN IRFR120 WIT H ASS EMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 1999 IN T HE ASS EMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO
IRF U120 12 916A 34
AS SEMBLY LOT CODE
DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A
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9
IRFR/U3410
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL
16.3 ( .641 ) 15.7 ( .619 )
16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Pulse width 300s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Starting TJ = 25C, L = 0.85mH
R G = 25, IAS = 18A.
ISD 18A, di/dt 360A/s, VDD V(BR)DSS,
TJ 175C
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
* When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.9/02
10
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